mirror of
https://github.com/MiyooCFW/buildroot.git
synced 2025-09-27 22:24:19 +03:00
bump version to 2022.02.9
add miyoo_defconfig
This commit is contained in:
tiopex
@@ -0,0 +1,40 @@
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From aaaa10b613165b7790fe1c084de007240b5bd77a Mon Sep 17 00:00:00 2001
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From: Neal Frager <neal.frager@amd.com>
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Date: Thu, 5 May 2022 13:34:43 +0100
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Subject: [PATCH 1/1] arm64: zynqmp: zynqmp-zcu102-revA: Fix DP PLL
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configuration
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This patch fixes the DP audio and video PLL configurations
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for the zynqmp-zcu106-revA evaluation board
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The Linux DP driver expects the DP to be using the following PLL config:
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- DP video PLL should use the VPLL (0x0)
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- DP audio PLL should use the RPLL (0x3)
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Register 0xFD1A0070 configures the DP video PLL.
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Register 0xFD1A0074 configures the DP audio PLL.
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Signed-off-by: Neal Frager <neal.frager@amd.com>
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Signed-off-by: Michal Simek <michal.simek@amd.com>
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---
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board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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diff --git a/board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c
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index 15f0be1a43..cbc436289f 100644
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--- a/board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c
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+++ b/board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c
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@@ -81,8 +81,8 @@ static unsigned long psu_clock_init_data(void)
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psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
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psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U);
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psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U);
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- psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010203U);
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- psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01013C00U);
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+ psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010500U);
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+ psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01013C03U);
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psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01011303U);
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psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
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psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
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--
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2.17.1
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562
board/zynqmp/zcu106/pm_cfg_obj.c
Normal file
562
board/zynqmp/zcu106/pm_cfg_obj.c
Normal file
@@ -0,0 +1,562 @@
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/******************************************************************************
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* Copyright (c) 2017 - 2021 Xilinx, Inc. All rights reserved.
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* SPDX-License-Identifier: MIT
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******************************************************************************/
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#include "xil_types.h"
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#include "pm_defs.h"
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#define PM_CONFIG_MASTER_SECTION_ID 0x101U
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#define PM_CONFIG_SLAVE_SECTION_ID 0x102U
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#define PM_CONFIG_PREALLOC_SECTION_ID 0x103U
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#define PM_CONFIG_POWER_SECTION_ID 0x104U
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#define PM_CONFIG_RESET_SECTION_ID 0x105U
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#define PM_CONFIG_SHUTDOWN_SECTION_ID 0x106U
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#define PM_CONFIG_SET_CONFIG_SECTION_ID 0x107U
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#define PM_CONFIG_GPO_SECTION_ID 0x108U
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#define PM_SLAVE_FLAG_IS_SHAREABLE 0x1U
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#define PM_MASTER_USING_SLAVE_MASK 0x2U
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#define PM_CONFIG_GPO1_MIO_PIN_34_MAP (1U << 10U)
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#define PM_CONFIG_GPO1_MIO_PIN_35_MAP (1U << 11U)
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#define PM_CONFIG_GPO1_MIO_PIN_36_MAP (1U << 12U)
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#define PM_CONFIG_GPO1_MIO_PIN_37_MAP (1U << 13U)
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#define PM_CONFIG_GPO1_BIT_2_MASK (1U << 2U)
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#define PM_CONFIG_GPO1_BIT_3_MASK (1U << 3U)
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#define PM_CONFIG_GPO1_BIT_4_MASK (1U << 4U)
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#define PM_CONFIG_GPO1_BIT_5_MASK (1U << 5U)
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#define SUSPEND_TIMEOUT 0xFFFFFFFFU
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#define PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK 0x00000001
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#define PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK 0x00000100
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#define PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK 0x00000200
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#if defined (__ICCARM__)
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#pragma language=save
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#pragma language=extended
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#endif
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#if defined (__GNUC__)
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const u32 XPm_ConfigObject[] __attribute__((used, section(".sys_cfg_data"))) =
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#elif defined (__ICCARM__)
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#pragma location = ".sys_cfg_data"
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__root const u32 XPm_ConfigObject[] =
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#endif
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{
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/**********************************************************************/
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/* HEADER */
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2, /* Number of remaining words in the header */
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8, /* Number of sections included in config object */
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1U, /* Type of config object as base */
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/**********************************************************************/
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/* MASTER SECTION */
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PM_CONFIG_MASTER_SECTION_ID, /* Master SectionID */
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3U, /* No. of Masters*/
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NODE_APU, /* Master Node ID */
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PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK, /* IPI Mask of this master */
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SUSPEND_TIMEOUT, /* Suspend timeout */
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PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* Suspend permissions */
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PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* Wake permissions */
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NODE_RPU_0, /* Master Node ID */
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PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK, /* IPI Mask of this master */
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SUSPEND_TIMEOUT, /* Suspend timeout */
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PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* Suspend permissions */
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PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* Wake permissions */
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NODE_RPU_1, /* Master Node ID */
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PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask of this master */
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SUSPEND_TIMEOUT, /* Suspend timeout */
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PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK, /* Suspend permissions */
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PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK, /* Wake permissions */
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/**********************************************************************/
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/* SLAVE SECTION */
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PM_CONFIG_SLAVE_SECTION_ID, /* Section ID */
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49, /* Number of slaves */
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NODE_OCM_BANK_0,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
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NODE_OCM_BANK_1,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
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NODE_OCM_BANK_2,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
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NODE_OCM_BANK_3,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
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NODE_TCM_0_A,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK, /* IPI Mask */
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NODE_TCM_0_B,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK, /* IPI Mask */
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NODE_TCM_1_A,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
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NODE_TCM_1_B,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
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NODE_L2,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
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NODE_GPU_PP_0,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
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NODE_GPU_PP_1,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
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NODE_USB_0,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
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NODE_USB_1,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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0U, /* IPI Mask */
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NODE_TTC_0,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
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NODE_TTC_1,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
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NODE_TTC_2,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
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NODE_TTC_3,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
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NODE_SATA,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
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NODE_ETH_0,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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0U, /* IPI Mask */
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NODE_ETH_1,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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0U, /* IPI Mask */
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NODE_ETH_2,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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0U, /* IPI Mask */
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NODE_ETH_3,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
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NODE_UART_0,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
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NODE_UART_1,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
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NODE_SPI_0,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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0U, /* IPI Mask */
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NODE_SPI_1,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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0U, /* IPI Mask */
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NODE_I2C_0,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
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NODE_I2C_1,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
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NODE_SD_0,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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0U, /* IPI Mask */
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NODE_SD_1,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
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||||
|
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NODE_DP,
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PM_SLAVE_FLAG_IS_SHAREABLE,
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PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
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|
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NODE_GDMA,
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PM_SLAVE_FLAG_IS_SHAREABLE,
|
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PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
|
||||
|
||||
NODE_ADMA,
|
||||
PM_SLAVE_FLAG_IS_SHAREABLE,
|
||||
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
|
||||
|
||||
NODE_NAND,
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||||
PM_SLAVE_FLAG_IS_SHAREABLE,
|
||||
0U, /* IPI Mask */
|
||||
|
||||
NODE_QSPI,
|
||||
PM_SLAVE_FLAG_IS_SHAREABLE,
|
||||
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
|
||||
|
||||
NODE_GPIO,
|
||||
PM_SLAVE_FLAG_IS_SHAREABLE,
|
||||
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
|
||||
|
||||
NODE_CAN_0,
|
||||
PM_SLAVE_FLAG_IS_SHAREABLE,
|
||||
0U, /* IPI Mask */
|
||||
|
||||
NODE_CAN_1,
|
||||
PM_SLAVE_FLAG_IS_SHAREABLE,
|
||||
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
|
||||
|
||||
NODE_EXTERN,
|
||||
PM_SLAVE_FLAG_IS_SHAREABLE,
|
||||
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
|
||||
|
||||
NODE_DDR,
|
||||
PM_SLAVE_FLAG_IS_SHAREABLE,
|
||||
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
|
||||
|
||||
NODE_IPI_APU,
|
||||
0U,
|
||||
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK, /* IPI Mask */
|
||||
|
||||
NODE_IPI_RPU_0,
|
||||
0U,
|
||||
PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK, /* IPI Mask */
|
||||
|
||||
NODE_IPI_RPU_1,
|
||||
0U,
|
||||
PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
|
||||
|
||||
NODE_GPU,
|
||||
PM_SLAVE_FLAG_IS_SHAREABLE,
|
||||
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
|
||||
|
||||
NODE_PCIE,
|
||||
PM_SLAVE_FLAG_IS_SHAREABLE,
|
||||
0U, /* IPI Mask */
|
||||
|
||||
NODE_PCAP,
|
||||
PM_SLAVE_FLAG_IS_SHAREABLE,
|
||||
0U, /* IPI Mask */
|
||||
|
||||
NODE_RTC,
|
||||
PM_SLAVE_FLAG_IS_SHAREABLE,
|
||||
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
|
||||
|
||||
NODE_VCU,
|
||||
PM_SLAVE_FLAG_IS_SHAREABLE,
|
||||
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
|
||||
|
||||
NODE_PL,
|
||||
PM_SLAVE_FLAG_IS_SHAREABLE,
|
||||
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
|
||||
|
||||
|
||||
/**********************************************************************/
|
||||
/* PREALLOC SECTION */
|
||||
|
||||
PM_CONFIG_PREALLOC_SECTION_ID, /* Preallaoc SectionID */
|
||||
3U, /* No. of Masters*/
|
||||
|
||||
/* Prealloc for psu_cortexa53_0 */
|
||||
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK,
|
||||
12,
|
||||
NODE_DDR,
|
||||
PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
|
||||
PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
|
||||
PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
|
||||
|
||||
NODE_L2,
|
||||
PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
|
||||
PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
|
||||
PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
|
||||
|
||||
NODE_OCM_BANK_0,
|
||||
PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
|
||||
PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
|
||||
PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
|
||||
|
||||
NODE_OCM_BANK_1,
|
||||
PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
|
||||
PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
|
||||
PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
|
||||
|
||||
NODE_OCM_BANK_2,
|
||||
PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
|
||||
PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
|
||||
PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
|
||||
|
||||
NODE_OCM_BANK_3,
|
||||
PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
|
||||
PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
|
||||
PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
|
||||
|
||||
NODE_I2C_0,
|
||||
PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
|
||||
PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
|
||||
PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
|
||||
|
||||
NODE_I2C_1,
|
||||
PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
|
||||
PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
|
||||
PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
|
||||
|
||||
NODE_SD_1,
|
||||
PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
|
||||
PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
|
||||
PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
|
||||
|
||||
NODE_QSPI,
|
||||
PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
|
||||
PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
|
||||
PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
|
||||
|
||||
NODE_PL,
|
||||
PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
|
||||
PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
|
||||
PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
|
||||
|
||||
NODE_IPI_APU,
|
||||
PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
|
||||
PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
|
||||
PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
|
||||
|
||||
|
||||
/* Prealloc for psu_cortexr5_0 */
|
||||
PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK,
|
||||
3,
|
||||
NODE_TCM_0_A,
|
||||
PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
|
||||
PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
|
||||
PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
|
||||
|
||||
NODE_TCM_0_B,
|
||||
PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
|
||||
PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
|
||||
PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
|
||||
|
||||
NODE_IPI_RPU_0,
|
||||
PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
|
||||
PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
|
||||
PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
|
||||
|
||||
|
||||
/* Prealloc for psu_cortexr5_1 */
|
||||
PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
3,
|
||||
NODE_TCM_1_A,
|
||||
PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
|
||||
PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
|
||||
PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
|
||||
|
||||
NODE_TCM_1_B,
|
||||
PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
|
||||
PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
|
||||
PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
|
||||
|
||||
NODE_IPI_RPU_1,
|
||||
PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
|
||||
PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
|
||||
PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
|
||||
|
||||
|
||||
|
||||
/**********************************************************************/
|
||||
/* POWER SECTION */
|
||||
|
||||
PM_CONFIG_POWER_SECTION_ID, /* Power Section ID */
|
||||
4U, /* Number of power nodes */
|
||||
|
||||
NODE_APU, /* Power node ID */
|
||||
PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* Force power down permissions */
|
||||
|
||||
NODE_RPU, /* Power node ID */
|
||||
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* Force power down permissions */
|
||||
|
||||
NODE_FPD, /* Power node ID */
|
||||
PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* Force power down permissions */
|
||||
|
||||
NODE_PLD, /* Power node ID */
|
||||
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* Force power down permissions */
|
||||
|
||||
|
||||
/**********************************************************************/
|
||||
/* RESET SECTION */
|
||||
|
||||
PM_CONFIG_RESET_SECTION_ID, /* Reset Section ID */
|
||||
120U, /* Number of resets */
|
||||
|
||||
XILPM_RESET_PCIE_CFG, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_PCIE_BRIDGE, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_PCIE_CTRL, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_DP, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_SWDT_CRF, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_AFI_FM5, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_AFI_FM4, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_AFI_FM3, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_AFI_FM2, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_AFI_FM1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_AFI_FM0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GDMA, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPU_PP1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPU_PP0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPU, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GT, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_SATA, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_ACPU3_PWRON, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_ACPU2_PWRON, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_ACPU1_PWRON, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_ACPU0_PWRON, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_APU_L2, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_ACPU3, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_ACPU2, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_ACPU1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_ACPU0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_DDR, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_APM_FPD, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_SOFT, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GEM0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GEM1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GEM2, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GEM3, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_QSPI, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_UART0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_UART1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_SPI0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_SPI1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_SDIO0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_SDIO1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_CAN0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_CAN1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_I2C0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_I2C1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_TTC0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_TTC1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_TTC2, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_TTC3, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_SWDT_CRL, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_NAND, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_ADMA, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPIO, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_IOU_CC, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_TIMESTAMP, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_RPU_R50, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_RPU_R51, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_RPU_AMBA, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_OCM, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_RPU_PGE, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_USB0_CORERESET, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_USB1_CORERESET, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_USB0_HIBERRESET, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_USB1_HIBERRESET, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_USB0_APB, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_USB1_APB, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_IPI, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_APM_LPD, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_RTC, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_SYSMON, 0,
|
||||
XILPM_RESET_AFI_FM6, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_LPD_SWDT, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_FPD, PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK,
|
||||
XILPM_RESET_RPU_DBG1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_RPU_DBG0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_DBG_LPD, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_DBG_FPD, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_APLL, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_DPLL, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_VPLL, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_IOPLL, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_RPLL, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPO3_PL_0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPO3_PL_1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPO3_PL_2, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPO3_PL_3, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPO3_PL_4, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPO3_PL_5, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPO3_PL_6, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPO3_PL_7, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPO3_PL_8, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPO3_PL_9, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPO3_PL_10, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPO3_PL_11, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPO3_PL_12, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPO3_PL_13, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPO3_PL_14, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPO3_PL_15, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPO3_PL_16, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPO3_PL_17, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPO3_PL_18, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPO3_PL_19, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPO3_PL_20, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPO3_PL_21, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPO3_PL_22, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPO3_PL_23, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPO3_PL_24, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPO3_PL_25, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPO3_PL_26, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPO3_PL_27, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPO3_PL_28, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPO3_PL_29, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPO3_PL_30, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPO3_PL_31, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_RPU_LS, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_PS_ONLY, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_PL, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPIO5_EMIO_92, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPIO5_EMIO_93, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPIO5_EMIO_94, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
XILPM_RESET_GPIO5_EMIO_95, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
|
||||
|
||||
/**********************************************************************/
|
||||
/* SET CONFIG SECTION */
|
||||
PM_CONFIG_SET_CONFIG_SECTION_ID, /* Set Config Section ID */
|
||||
0U, /* Permissions to load base config object */
|
||||
0U, /* Permissions to load overlay config object */
|
||||
|
||||
/**********************************************************************/
|
||||
/* SHUTDOWN SECTION */
|
||||
|
||||
PM_CONFIG_SHUTDOWN_SECTION_ID, /* Shutdown Section ID */
|
||||
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* System Shutdown/Restart Permission */
|
||||
|
||||
/**********************************************************************/
|
||||
/* GPO SECTION */
|
||||
PM_CONFIG_GPO_SECTION_ID, /* GPO Section ID */
|
||||
PM_CONFIG_GPO1_MIO_PIN_34_MAP |
|
||||
PM_CONFIG_GPO1_MIO_PIN_35_MAP |
|
||||
PM_CONFIG_GPO1_MIO_PIN_36_MAP |
|
||||
PM_CONFIG_GPO1_MIO_PIN_37_MAP |
|
||||
0, /* State of GPO pins */
|
||||
};
|
||||
#if defined (__ICCARM__)
|
||||
#pragma language=restore
|
||||
#endif
|
||||
|
||||
1
board/zynqmp/zcu106/uboot.fragment
Normal file
1
board/zynqmp/zcu106/uboot.fragment
Normal file
@@ -0,0 +1 @@
|
||||
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu106-revA"
|
||||
Reference in New Issue
Block a user