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https://github.com/MiyooCFW/buildroot.git
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bump version to 2022.02.9
add miyoo_defconfig
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tiopex
156
package/safeclib/0001-fix-armv7-asm-inline-error-GH-115.patch
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156
package/safeclib/0001-fix-armv7-asm-inline-error-GH-115.patch
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@@ -0,0 +1,156 @@
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From 9c739800a8915d5f2a73c840190920e95ffa1c5c Mon Sep 17 00:00:00 2001
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From: Reini Urban <rurban@cpan.org>
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Date: Fri, 18 Feb 2022 09:46:45 +0100
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Subject: [PATCH] fix armv7 asm inline error GH #115
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some armv7 buildroot variants fail on asm.
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we already probe for that, so use it.
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Fixes GH #115
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[Retrieved from:
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https://github.com/rurban/safeclib/commit/9c739800a8915d5f2a73c840190920e95ffa1c5c]
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Signed-off-by: Fabrice Fontaine <fontaine.fabrice@gmail.com>
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---
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tests/perf_private.h | 49 +++++++++++++++++++++++++-------------------
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1 file changed, 28 insertions(+), 21 deletions(-)
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diff --git a/tests/perf_private.h b/tests/perf_private.h
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index 3296cb3d..843674d3 100644
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--- a/tests/perf_private.h
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+++ b/tests/perf_private.h
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@@ -1,9 +1,9 @@
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/*------------------------------------------------------------------
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* perf_private.h - Internal benchmarking tools
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*
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- * 2020 Reini Urban
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+ * 2020,2022 Reini Urban
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*
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- * Copyright (c) 2017, 2020 Reini Urban
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+ * Copyright (c) 2017, 2020, 2022 Reini Urban
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* All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person
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@@ -55,13 +55,16 @@ static inline uint64_t timer_start();
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static inline uint64_t timer_end();
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static inline clock_t rdtsc() {
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-#ifdef __x86_64__
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+#ifndef ASM_INLINE
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+#define NO_CYCLE_COUNTER
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+ return clock();
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+#elif defined __x86_64__
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uint64_t a, d;
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- __asm__ volatile("rdtsc" : "=a"(a), "=d"(d));
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+ ASM_INLINE volatile("rdtsc" : "=a"(a), "=d"(d));
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return (clock_t)(a | (d << 32));
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#elif defined(__i386__)
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clock_t x;
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- __asm__ volatile("rdtsc" : "=A"(x));
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+ ASM_INLINE volatile("rdtsc" : "=A"(x));
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return x;
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#elif defined(__ARM_ARCH) && (__ARM_ARCH >= 7) && (SIZEOF_SIZE_T == 4)
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// V7 is the earliest arch that has a standard cyclecount (some say 6)
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@@ -69,11 +72,11 @@ static inline clock_t rdtsc() {
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uint32_t pmuseren;
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uint32_t pmcntenset;
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// Read the user mode perf monitor counter access permissions.
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- asm volatile("mrc p15, 0, %0, c9, c14, 0" : "=r"(pmuseren));
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+ ASM_INLINE volatile("mrc p15, 0, %0, c9, c14, 0" : "=r"(pmuseren));
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if (pmuseren & 1) { // Allows reading perfmon counters for user mode code.
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- asm volatile("mrc p15, 0, %0, c9, c12, 1" : "=r"(pmcntenset));
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+ ASM_INLINE volatile("mrc p15, 0, %0, c9, c12, 1" : "=r"(pmcntenset));
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if (pmcntenset & 0x80000000ul) { // Is it counting?
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- asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r"(pmccntr));
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+ ASM_INLINE volatile("mrc p15, 0, %0, c9, c13, 0" : "=r"(pmccntr));
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// The counter is set up to count every 64th cycle
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return (int64_t)(pmccntr) * 64; // Should optimize to << 6
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}
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@@ -83,22 +86,22 @@ static inline clock_t rdtsc() {
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uint64_t pmccntr;
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uint64_t pmuseren = 1UL;
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// Read the user mode perf monitor counter access permissions.
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- //asm volatile("mrs cntv_ctl_el0, %0" : "=r" (pmuseren));
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+ //ASM_INLINE volatile("mrs cntv_ctl_el0, %0" : "=r" (pmuseren));
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if (pmuseren & 1) { // Allows reading perfmon counters for user mode code.
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- asm volatile("mrs %0, cntvct_el0" : "=r" (pmccntr));
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+ ASM_INLINE volatile("mrs %0, cntvct_el0" : "=r" (pmccntr));
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return (uint64_t)(pmccntr) * 64; // Should optimize to << 6
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}
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return (uint64_t)rdtsc();
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#elif defined(__powerpc64__) || defined(__ppc64__)
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uint64_t tb;
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- __asm__ volatile (\
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+ ASM_INLINE volatile (\
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"mfspr %0, 268"
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: "=r" (tb));
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return tb;
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#elif defined(__powerpc__) || defined(__ppc__)
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// This returns a time-base, which is not always precisely a cycle-count.
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uint32_t tbu, tbl, tmp;
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- __asm__ volatile (\
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+ ASM_INLINE volatile (\
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"0:\n"
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"mftbu %0\n"
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"mftbl %1\n"
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@@ -109,12 +112,12 @@ static inline clock_t rdtsc() {
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return (((uint64_t) tbu << 32) | tbl);
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#elif defined(__sparc__)
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uint64_t tick;
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- asm(".byte 0x83, 0x41, 0x00, 0x00");
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- asm("mov %%g1, %0" : "=r" (tick));
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+ ASM_INLINE(".byte 0x83, 0x41, 0x00, 0x00");
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+ ASM_INLINE("mov %%g1, %0" : "=r" (tick));
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return tick;
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#elif defined(__ia64__)
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uint64_t itc;
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- asm("mov %0 = ar.itc" : "=r" (itc));
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+ ASM_INLINE("mov %0 = ar.itc" : "=r" (itc));
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return itc;
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#else
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#define NO_CYCLE_COUNTER
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@@ -126,9 +129,11 @@ static inline clock_t rdtsc() {
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// 3.2.1 The Improved Benchmarking Method
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static inline uint64_t timer_start()
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{
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-#if defined (__i386__) || (defined(__x86_64__) && SIZEOF_SIZE_T == 4)
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+#ifndef ASM_INLINE
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+ return (uint64_t)rdtsc();
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+#elif defined (__i386__) || (defined(__x86_64__) && SIZEOF_SIZE_T == 4)
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uint32_t cycles_high, cycles_low;
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- __asm__ volatile
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+ ASM_INLINE volatile
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("cpuid\n\t"
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"rdtsc\n\t"
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"mov %%edx, %0\n\t"
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@@ -137,7 +142,7 @@ static inline uint64_t timer_start()
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return ((uint64_t)cycles_high << 32) | cycles_low;
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#elif defined __x86_64__
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uint32_t cycles_high, cycles_low;
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- __asm__ volatile
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+ ASM_INLINE volatile
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("cpuid\n\t"
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"rdtsc\n\t"
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"mov %%edx, %0\n\t"
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@@ -151,9 +156,11 @@ static inline uint64_t timer_start()
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static inline uint64_t timer_end()
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{
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-#if defined (__i386__) || (defined(__x86_64__) && defined (HAVE_BIT32))
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+#ifndef ASM_INLINE
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+ return (uint64_t)rdtsc();
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+#elif defined (__i386__) || (defined(__x86_64__) && defined (HAVE_BIT32))
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uint32_t cycles_high, cycles_low;
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- __asm__ volatile
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+ ASM_INLINE volatile
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("rdtscp\n\t"
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"mov %%edx, %0\n\t"
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"mov %%eax, %1\n\t"
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@@ -162,7 +169,7 @@ static inline uint64_t timer_end()
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return ((uint64_t)cycles_high << 32) | cycles_low;
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#elif defined __x86_64__
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uint32_t cycles_high, cycles_low;
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- __asm__ volatile
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+ ASM_INLINE volatile
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("rdtscp\n\t"
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"mov %%edx, %0\n\t"
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"mov %%eax, %1\n\t"
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@@ -1,5 +1,5 @@
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# From https://github.com/rurban/safeclib/releases/tag/v08112019
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sha256 bc2f25875522c50a3a5901981020d906db0b6a7d365619b8d72412c126be3923 libsafec-08112019.0-gad76c7.tar.bz2
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# From https://github.com/rurban/safeclib/releases/tag/v3.7.1
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sha256 71d3ec970f930bd980f2a41127228eeedfc53749e4c6b203329adc4ff7df32a7 safeclib-3.7.1.tar.xz
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# Hash for license file
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sha256 c33e77efd5781e3d59a2bb648c82d2a615035ef0d24cf58880380e3af906510b COPYING
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sha256 c33e77efd5781e3d59a2bb648c82d2a615035ef0d24cf58880380e3af906510b COPYING
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@@ -4,12 +4,16 @@
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#
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################################################################################
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SAFECLIB_VERSION = 08112019
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SAFECLIB_VERSION = 3.7.1
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SAFECLIB_SITE = \
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https://github.com/rurban/safeclib/releases/download/v$(SAFECLIB_VERSION)
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SAFECLIB_SOURCE = libsafec-$(SAFECLIB_VERSION).0-gad76c7.tar.bz2
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SAFECLIB_SOURCE = safeclib-$(SAFECLIB_VERSION).tar.xz
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SAFECLIB_LICENSE = MIT
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SAFECLIB_LICENSE_FILES = COPYING
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SAFECLIB_INSTALL_STAGING = YES
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SAFECLIB_CONF_ENV = CFLAGS="$(TARGET_CFLAGS) -std=c99"
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# -fstack-protector-strong is used by default. Disable that so the
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# BR2_SSP_* options in the toolchain wrapper are used instead
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SAFECLIB_CONF_OPTS = --disable-hardening
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$(eval $(autotools-package))
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