da7b6e47c7
This includes the files as of wget http://www.fischl.de/usbasp/usbasp.2011-05-28.tar.gz tar -xf usbasp.2011.05-28.tar.gz
337 lines
6.2 KiB
C
Executable File
337 lines
6.2 KiB
C
Executable File
/*
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* isp.c - part of USBasp
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*
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* Autor..........: Thomas Fischl <tfischl@gmx.de>
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* Description....: Provides functions for communication/programming
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* over ISP interface
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* Licence........: GNU GPL v2 (see Readme.txt)
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* Creation Date..: 2005-02-23
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* Last change....: 2010-01-19
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*/
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#include <avr/io.h>
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#include "isp.h"
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#include "clock.h"
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#include "usbasp.h"
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#define spiHWdisable() SPCR = 0
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uchar sck_sw_delay;
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uchar sck_spcr;
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uchar sck_spsr;
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uchar isp_hiaddr;
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void spiHWenable() {
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SPCR = sck_spcr;
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SPSR = sck_spsr;
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}
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void ispSetSCKOption(uchar option) {
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if (option == USBASP_ISP_SCK_AUTO)
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option = USBASP_ISP_SCK_375;
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if (option >= USBASP_ISP_SCK_93_75) {
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ispTransmit = ispTransmit_hw;
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sck_spsr = 0;
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sck_sw_delay = 1; /* force RST#/SCK pulse for 320us */
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switch (option) {
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case USBASP_ISP_SCK_1500:
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/* enable SPI, master, 1.5MHz, XTAL/8 */
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sck_spcr = (1 << SPE) | (1 << MSTR) | (1 << SPR0);
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sck_spsr = (1 << SPI2X);
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case USBASP_ISP_SCK_750:
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/* enable SPI, master, 750kHz, XTAL/16 */
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sck_spcr = (1 << SPE) | (1 << MSTR) | (1 << SPR0);
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break;
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case USBASP_ISP_SCK_375:
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default:
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/* enable SPI, master, 375kHz, XTAL/32 (default) */
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sck_spcr = (1 << SPE) | (1 << MSTR) | (1 << SPR1);
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sck_spsr = (1 << SPI2X);
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break;
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case USBASP_ISP_SCK_187_5:
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/* enable SPI, master, 187.5kHz XTAL/64 */
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sck_spcr = (1 << SPE) | (1 << MSTR) | (1 << SPR1);
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break;
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case USBASP_ISP_SCK_93_75:
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/* enable SPI, master, 93.75kHz XTAL/128 */
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sck_spcr = (1 << SPE) | (1 << MSTR) | (1 << SPR1) | (1 << SPR0);
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break;
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}
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} else {
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ispTransmit = ispTransmit_sw;
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switch (option) {
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case USBASP_ISP_SCK_32:
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sck_sw_delay = 3;
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break;
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case USBASP_ISP_SCK_16:
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sck_sw_delay = 6;
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break;
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case USBASP_ISP_SCK_8:
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sck_sw_delay = 12;
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break;
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case USBASP_ISP_SCK_4:
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sck_sw_delay = 24;
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break;
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case USBASP_ISP_SCK_2:
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sck_sw_delay = 48;
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break;
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case USBASP_ISP_SCK_1:
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sck_sw_delay = 96;
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break;
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case USBASP_ISP_SCK_0_5:
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sck_sw_delay = 192;
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break;
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}
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}
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}
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void ispDelay() {
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uint8_t starttime = TIMERVALUE;
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while ((uint8_t) (TIMERVALUE - starttime) < sck_sw_delay) {
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}
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}
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void ispConnect() {
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/* all ISP pins are inputs before */
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/* now set output pins */
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ISP_DDR |= (1 << ISP_RST) | (1 << ISP_SCK) | (1 << ISP_MOSI);
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/* reset device */
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ISP_OUT &= ~(1 << ISP_RST); /* RST low */
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ISP_OUT &= ~(1 << ISP_SCK); /* SCK low */
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/* positive reset pulse > 2 SCK (target) */
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ispDelay();
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ISP_OUT |= (1 << ISP_RST); /* RST high */
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ispDelay();
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ISP_OUT &= ~(1 << ISP_RST); /* RST low */
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if (ispTransmit == ispTransmit_hw) {
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spiHWenable();
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}
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/* Initial extended address value */
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isp_hiaddr = 0;
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}
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void ispDisconnect() {
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/* set all ISP pins inputs */
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ISP_DDR &= ~((1 << ISP_RST) | (1 << ISP_SCK) | (1 << ISP_MOSI));
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/* switch pullups off */
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ISP_OUT &= ~((1 << ISP_RST) | (1 << ISP_SCK) | (1 << ISP_MOSI));
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/* disable hardware SPI */
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spiHWdisable();
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}
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uchar ispTransmit_sw(uchar send_byte) {
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uchar rec_byte = 0;
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uchar i;
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for (i = 0; i < 8; i++) {
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/* set MSB to MOSI-pin */
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if ((send_byte & 0x80) != 0) {
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ISP_OUT |= (1 << ISP_MOSI); /* MOSI high */
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} else {
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ISP_OUT &= ~(1 << ISP_MOSI); /* MOSI low */
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}
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/* shift to next bit */
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send_byte = send_byte << 1;
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/* receive data */
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rec_byte = rec_byte << 1;
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if ((ISP_IN & (1 << ISP_MISO)) != 0) {
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rec_byte++;
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}
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/* pulse SCK */
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ISP_OUT |= (1 << ISP_SCK); /* SCK high */
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ispDelay();
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ISP_OUT &= ~(1 << ISP_SCK); /* SCK low */
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ispDelay();
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}
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return rec_byte;
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}
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uchar ispTransmit_hw(uchar send_byte) {
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SPDR = send_byte;
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while (!(SPSR & (1 << SPIF)))
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;
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return SPDR;
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}
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uchar ispEnterProgrammingMode() {
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uchar check;
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uchar count = 32;
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while (count--) {
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ispTransmit(0xAC);
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ispTransmit(0x53);
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check = ispTransmit(0);
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ispTransmit(0);
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if (check == 0x53) {
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return 0;
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}
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spiHWdisable();
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/* pulse RST */
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ispDelay();
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ISP_OUT |= (1 << ISP_RST); /* RST high */
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ispDelay();
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ISP_OUT &= ~(1 << ISP_RST); /* RST low */
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ispDelay();
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if (ispTransmit == ispTransmit_hw) {
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spiHWenable();
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}
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}
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return 1; /* error: device dosn't answer */
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}
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static void ispUpdateExtended(unsigned long address)
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{
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uchar curr_hiaddr;
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curr_hiaddr = (address >> 17);
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/* check if extended address byte is changed */
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if(isp_hiaddr != curr_hiaddr)
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{
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isp_hiaddr = curr_hiaddr;
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/* Load Extended Address byte */
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ispTransmit(0x4D);
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ispTransmit(0x00);
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ispTransmit(isp_hiaddr);
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ispTransmit(0x00);
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}
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}
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uchar ispReadFlash(unsigned long address) {
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ispUpdateExtended(address);
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ispTransmit(0x20 | ((address & 1) << 3));
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ispTransmit(address >> 9);
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ispTransmit(address >> 1);
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return ispTransmit(0);
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}
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uchar ispWriteFlash(unsigned long address, uchar data, uchar pollmode) {
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/* 0xFF is value after chip erase, so skip programming
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if (data == 0xFF) {
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return 0;
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}
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*/
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ispUpdateExtended(address);
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ispTransmit(0x40 | ((address & 1) << 3));
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ispTransmit(address >> 9);
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ispTransmit(address >> 1);
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ispTransmit(data);
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if (pollmode == 0)
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return 0;
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if (data == 0x7F) {
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clockWait(15); /* wait 4,8 ms */
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return 0;
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} else {
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/* polling flash */
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uchar retries = 30;
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uint8_t starttime = TIMERVALUE;
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while (retries != 0) {
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if (ispReadFlash(address) != 0x7F) {
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return 0;
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};
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if ((uint8_t) (TIMERVALUE - starttime) > CLOCK_T_320us) {
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starttime = TIMERVALUE;
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retries--;
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}
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}
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return 1; /* error */
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}
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}
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uchar ispFlushPage(unsigned long address, uchar pollvalue) {
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ispUpdateExtended(address);
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ispTransmit(0x4C);
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ispTransmit(address >> 9);
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ispTransmit(address >> 1);
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ispTransmit(0);
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if (pollvalue == 0xFF) {
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clockWait(15);
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return 0;
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} else {
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/* polling flash */
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uchar retries = 30;
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uint8_t starttime = TIMERVALUE;
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while (retries != 0) {
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if (ispReadFlash(address) != 0xFF) {
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return 0;
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};
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if ((uint8_t) (TIMERVALUE - starttime) > CLOCK_T_320us) {
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starttime = TIMERVALUE;
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retries--;
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}
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}
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return 1; /* error */
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}
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}
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uchar ispReadEEPROM(unsigned int address) {
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ispTransmit(0xA0);
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ispTransmit(address >> 8);
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ispTransmit(address);
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return ispTransmit(0);
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}
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uchar ispWriteEEPROM(unsigned int address, uchar data) {
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ispTransmit(0xC0);
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ispTransmit(address >> 8);
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ispTransmit(address);
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ispTransmit(data);
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clockWait(30); // wait 9,6 ms
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return 0;
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}
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