mirror of
https://github.com/pjreddie/darknet.git
synced 2023-08-10 21:13:14 +03:00
Fixed nan issue for training with CUDNN_HALF=1 by using Tensor Cores
This commit is contained in:
AlexeyAB
@ -138,7 +138,9 @@ void fast_binarize_weights_gpu(float *weights, int n, int size, float *binary, f
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__global__ void cuda_f32_to_f16(float* input_f32, size_t size, half *output_f16)
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{
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int idx = blockIdx.x * blockDim.x + threadIdx.x;
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if (idx < size) output_f16[idx] = __float2half(input_f32[idx]);
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//if (idx < size) output_f16[idx] = __float2half(input_f32[idx]);
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if (idx < size) output_f16[idx] = __float2half_rn(input_f32[idx]);
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// __float2half_ru, __float2half_rd, __float2half_rz, __float2half_rn
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//if (idx < size) *((unsigned short *)output_f16 + idx) = __float2half(input_f32[idx]);
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}
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@ -290,113 +292,128 @@ void forward_convolutional_layer_gpu(convolutional_layer l, network_state state)
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float one = 1; // alpha[0], beta[0] is float for HALF and FLOAT
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float alpha = 1, beta = 0;
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#ifdef CUDNN_HALF
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// Note: For improved performance it is advised to use beta[0] = 0.0.
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// For Tensor Core: cudnnSetConvolutionMathType() where cudnnMathType_t mathType = CUDNN_TENSOR_OP_MATH;
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// 1. or CUDNN_CONVOLUTION_FWD_ALGO_IMPLICIT_PRECOMP_GEMM and use CUDNN_DATA_HALF
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// 2. or CUDNN_CONVOLUTION_FWD_ALGO_WINOGRAD_NONFUSED
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// More: http://docs.nvidia.com/deeplearning/sdk/cudnn-developer-guide/index.html#tensor_ops
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const size_t input16_size = l.batch*l.c*l.w*l.h;
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const size_t output16_size = l.batch*l.out_c*l.out_h*l.out_w;
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if (*state.net.max_input16_size < input16_size) {
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//printf("\n input16_size: cur = %zu \t max = %zu \n", input16_size, *state.net.max_input16_size);
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*state.net.max_input16_size = input16_size;
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if (*state.net.input16_gpu) cuda_free(*state.net.input16_gpu);
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*state.net.input16_gpu = (float *)cuda_make_f16_from_f32_array(NULL, *state.net.max_input16_size);
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}
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float *input16 = *state.net.input16_gpu;
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if (*state.net.max_output16_size < output16_size) {
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*state.net.max_output16_size = output16_size;
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if (*state.net.output16_gpu) cuda_free(*state.net.output16_gpu);
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*state.net.output16_gpu = (float *)cuda_make_f16_from_f32_array(NULL, *state.net.max_output16_size);
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}
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float *output16 = *state.net.output16_gpu;
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cuda_convert_f32_to_f16(state.input, input16_size, input16);
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//fill_ongpu(output16_size / 2, 0, (float *)output16, 1);
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cudnnConvolutionForward(cudnn_handle(),
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&alpha,
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l.srcTensorDesc,
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input16,
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l.weightDesc,
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l.weights_gpu16,
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l.convDesc,
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l.fw_algo,
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state.workspace,
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l.workspace_size,
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&beta,
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l.dstTensorDesc,
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output16);
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if (l.batch_normalize)
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//#ifdef CUDNN_HALF
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//if (state.use_mixed_precision) {
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int iteration_num = (*state.net.seen) / (state.net.batch*state.net.subdivisions);
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if(state.index != 0 && state.net.cudnn_half && !l.xnor && (!state.train || iteration_num > state.net.burn_in))
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{
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if (state.train) // Training
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{
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copy_ongpu(l.outputs*l.batch / 2, output16, 1, l.x_gpu, 1);
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//cudaMemcpyAsync(l.x_gpu, output16, l.outputs*l.batch*sizeof(half), cudaMemcpyDefault, get_cuda_stream());
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float one = 1;
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float zero = 0;
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// Batch-normalization can still take FP16 inputs and outputs, saving half the bandwidth
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// compared to FP32, it<69>s just that the statistics and value adjustment should be done in FP32.
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cudnnBatchNormalizationForwardTraining(cudnn_handle(),
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CUDNN_BATCHNORM_SPATIAL,
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&one,
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&zero,
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l.normDstTensorDescF16,
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l.x_gpu, // input
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l.normDstTensorDescF16,
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output16, // output
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l.normTensorDesc,
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l.scales_gpu,
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l.biases_gpu,
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.01,
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l.rolling_mean_gpu, // output (should be FP32)
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l.rolling_variance_gpu, // output (should be FP32)
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.00001,
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l.mean_gpu, // output (should be FP32)
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l.variance_gpu); // output (should be FP32)
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//printf("\n CUDNN_HALF!!! state.index = %d \n", state.index);
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cuda_convert_f16_to_f32(output16, output16_size, l.output_gpu);
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//forward_batchnorm_layer_gpu(l, state);
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// Note: For improved performance it is advised to use beta[0] = 0.0.
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// For Tensor Core: cudnnSetConvolutionMathType() where cudnnMathType_t mathType = CUDNN_TENSOR_OP_MATH;
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// 1. or CUDNN_CONVOLUTION_FWD_ALGO_IMPLICIT_PRECOMP_GEMM and use CUDNN_DATA_HALF
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// 2. or CUDNN_CONVOLUTION_FWD_ALGO_WINOGRAD_NONFUSED
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// More: http://docs.nvidia.com/deeplearning/sdk/cudnn-developer-guide/index.html#tensor_ops
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const size_t input16_size = l.batch*l.c*l.w*l.h;
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const size_t output16_size = l.batch*l.out_c*l.out_h*l.out_w;
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if (*state.net.max_input16_size < input16_size) {
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//printf("\n input16_size: cur = %zu \t max = %zu \n", input16_size, *state.net.max_input16_size);
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*state.net.max_input16_size = input16_size;
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if (*state.net.input16_gpu) cuda_free(*state.net.input16_gpu);
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*state.net.input16_gpu = (float *)cuda_make_f16_from_f32_array(NULL, *state.net.max_input16_size);
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}
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else // Detection
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float *input16 = *state.net.input16_gpu;
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if (*state.net.max_output16_size < output16_size) {
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*state.net.max_output16_size = output16_size;
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if (*state.net.output16_gpu) cuda_free(*state.net.output16_gpu);
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*state.net.output16_gpu = (float *)cuda_make_f16_from_f32_array(NULL, *state.net.max_output16_size);
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}
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float *output16 = *state.net.output16_gpu;
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cuda_convert_f32_to_f16(state.input, input16_size, input16);
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//fill_ongpu(output16_size / 2, 0, (float *)output16, 1);
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cudnnConvolutionForward(cudnn_handle(),
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&alpha,
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l.srcTensorDesc16,
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input16,
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l.weightDesc16,
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l.weights_gpu16,
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l.convDesc,
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l.fw_algo16,
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state.workspace,
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l.workspace_size,
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&beta,
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l.dstTensorDesc16,
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output16);
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if (l.batch_normalize)
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{
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if (state.train) // Training
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{
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copy_ongpu(l.outputs*l.batch / 2, output16, 1, l.x_gpu, 1);
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//cudaMemcpyAsync(l.x_gpu, output16, l.outputs*l.batch*sizeof(half), cudaMemcpyDefault, get_cuda_stream());
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float one = 1;
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float zero = 0;
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// Batch-normalization can still take FP16 inputs and outputs, saving half the bandwidth
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// compared to FP32, it<69>s just that the statistics and value adjustment should be done in FP32.
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cudnnBatchNormalizationForwardTraining(cudnn_handle(),
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CUDNN_BATCHNORM_SPATIAL,
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&one,
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&zero,
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l.normDstTensorDescF16,
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l.x_gpu, // input
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l.normDstTensorDescF16,
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output16, // output
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l.normTensorDesc,
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l.scales_gpu,
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l.biases_gpu,
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.01,
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l.rolling_mean_gpu, // output (should be FP32)
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l.rolling_variance_gpu, // output (should be FP32)
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.00001,
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l.mean_gpu, // output (should be FP32)
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l.variance_gpu); // output (should be FP32)
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cuda_convert_f16_to_f32(output16, output16_size, l.output_gpu);
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//forward_batchnorm_layer_gpu(l, state);
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}
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else // Detection
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{
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cuda_convert_f16_to_f32(output16, output16_size, l.output_gpu);
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normalize_gpu(l.output_gpu, l.rolling_mean_gpu, l.rolling_variance_gpu, l.batch, l.out_c, l.out_h*l.out_w);
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scale_bias_gpu(l.output_gpu, l.scales_gpu, l.batch, l.out_c, l.out_h*l.out_w);
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add_bias_gpu(l.output_gpu, l.biases_gpu, l.batch, l.out_c, l.out_w*l.out_h);
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}
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}
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else // BIAS only
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{
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cuda_convert_f16_to_f32(output16, output16_size, l.output_gpu);
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normalize_gpu(l.output_gpu, l.rolling_mean_gpu, l.rolling_variance_gpu, l.batch, l.out_c, l.out_h*l.out_w);
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scale_bias_gpu(l.output_gpu, l.scales_gpu, l.batch, l.out_c, l.out_h*l.out_w);
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add_bias_gpu(l.output_gpu, l.biases_gpu, l.batch, l.out_c, l.out_w*l.out_h);
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add_bias_gpu(l.output_gpu, l.biases_gpu, l.batch, l.n, l.out_w*l.out_h);
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}
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}
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else // BIAS only
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{
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cuda_convert_f16_to_f32(output16, output16_size, l.output_gpu);
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add_bias_gpu(l.output_gpu, l.biases_gpu, l.batch, l.n, l.out_w*l.out_h);
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else {
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//#else
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cudnnConvolutionForward(cudnn_handle(),
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&alpha, //&one,
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l.srcTensorDesc,
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state.input,
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l.weightDesc,
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l.weights_gpu,
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l.convDesc,
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l.fw_algo,
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state.workspace,
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l.workspace_size,
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&beta, //&one,
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l.dstTensorDesc,
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l.output_gpu);
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//cudaDeviceSynchronize();
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if (l.batch_normalize) {
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forward_batchnorm_layer_gpu(l, state);
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}
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else {
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add_bias_gpu(l.output_gpu, l.biases_gpu, l.batch, l.n, l.out_w*l.out_h);
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}
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//#endif // CUDNN_HALF
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}
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#else
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cudnnConvolutionForward(cudnn_handle(),
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&alpha, //&one,
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l.srcTensorDesc,
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state.input,
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l.weightDesc,
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l.weights_gpu,
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l.convDesc,
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l.fw_algo,
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state.workspace,
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l.workspace_size,
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&beta, //&one,
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l.dstTensorDesc,
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l.output_gpu);
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//cudaDeviceSynchronize();
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#endif // CUDNN_HALF
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#else
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fill_ongpu(l.outputs*l.batch, 0, l.output_gpu, 1);
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@ -418,16 +435,17 @@ void forward_convolutional_layer_gpu(convolutional_layer l, network_state state)
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}
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gemm_ongpu(0,0,m,n,k,1.,a,k,b,n,1.,c+i*m*n,n);
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}
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#endif
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#ifndef CUDNN_HALF
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if (l.batch_normalize) {
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forward_batchnorm_layer_gpu(l, state);
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}
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else {
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add_bias_gpu(l.output_gpu, l.biases_gpu, l.batch, l.n, l.out_w*l.out_h);
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}
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#endif // no CUDNN_HALF
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#endif
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//#ifndef CUDNN_HALF
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//#endif // no CUDNN_HALF
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if (l.activation != LINEAR) activate_array_ongpu(l.output_gpu, l.outputs*l.batch, l.activation);
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//if(l.dot > 0) dot_error_gpu(l);
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@ -441,13 +459,13 @@ void backward_convolutional_layer_gpu(convolutional_layer l, network_state state
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backward_bias_gpu(l.bias_updates_gpu, l.delta_gpu, l.batch, l.n, l.out_w*l.out_h);
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#ifndef CUDNN_HALF
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if(l.batch_normalize){
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backward_batchnorm_layer_gpu(l, state);
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} else {
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//backward_bias_gpu(l.bias_updates_gpu, l.delta_gpu, l.batch, l.n, l.out_w*l.out_h);
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}
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#endif // no CUDNN_HALF
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//#ifndef CUDNN_HALF
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//if(l.batch_normalize){
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// backward_batchnorm_layer_gpu(l, state);
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//} else {
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// //backward_bias_gpu(l.bias_updates_gpu, l.delta_gpu, l.batch, l.n, l.out_w*l.out_h);
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//}
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//#endif // no CUDNN_HALF
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float *original_input = state.input;
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if(l.xnor) state.input = l.binary_input_gpu;
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@ -455,117 +473,126 @@ void backward_convolutional_layer_gpu(convolutional_layer l, network_state state
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float one = 1;
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float alpha = 1, beta = 0;
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#ifdef CUDNN_HALF
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const size_t input16_size = l.batch*l.c*l.w*l.h;
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const size_t delta16_size = l.batch*l.n*l.out_w*l.out_h;
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if (*state.net.max_input16_size < input16_size) {
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*state.net.max_input16_size = input16_size;
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if(*state.net.input16_gpu) cuda_free(*state.net.input16_gpu);
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*state.net.input16_gpu = (float *)cuda_make_f16_from_f32_array(NULL, *state.net.max_input16_size);
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}
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float *input16 = *state.net.input16_gpu;
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if (*state.net.max_output16_size < delta16_size) {
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*state.net.max_output16_size = delta16_size;
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if(*state.net.output16_gpu) cuda_free(*state.net.output16_gpu);
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*state.net.output16_gpu = (float *)cuda_make_f16_from_f32_array(NULL, *state.net.max_output16_size);
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}
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float *delta16 = *state.net.output16_gpu;
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cuda_convert_f32_to_f16(state.input, input16_size, input16);
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cuda_convert_f32_to_f16(l.delta_gpu, delta16_size, delta16);
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if (l.batch_normalize) {
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//if (!state.train) {
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// l.mean_gpu = l.rolling_mean_gpu;
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// l.variance_gpu = l.rolling_variance_gpu;
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//}
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float one = 1;
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float zero = 0;
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cudnnBatchNormalizationBackward(cudnn_handle(),
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CUDNN_BATCHNORM_SPATIAL,
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&one,
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&zero,
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&one,
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&one,
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l.normDstTensorDescF16,
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l.x_gpu, // input
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l.normDstTensorDescF16,
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delta16, // input
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l.normDstTensorDescF16,
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l.x_norm_gpu, // output
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l.normTensorDesc,
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l.scales_gpu, // output (should be FP32)
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l.scale_updates_gpu, // output (should be FP32)
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l.bias_updates_gpu, // output (should be FP32)
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.00001,
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l.mean_gpu, // input (should be FP32)
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l.variance_gpu); // input (should be FP32)
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copy_ongpu(l.outputs*l.batch / 2, l.x_norm_gpu, 1, delta16, 1);
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//cudaMemcpyAsync(delta16, l.x_norm_gpu, l.outputs*l.batch * sizeof(half), cudaMemcpyDefault, get_cuda_stream());
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}
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else
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//#ifdef CUDNN_HALF
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int iteration_num = (*state.net.seen) / (state.net.batch*state.net.subdivisions);
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if (state.index != 0 && state.net.cudnn_half && !l.xnor && (!state.train || iteration_num > state.net.burn_in))
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{
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//backward_bias_gpu(l.bias_updates_gpu, l.delta_gpu, l.batch, l.n, l.out_w*l.out_h);
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}
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// convert input: state.input (x), l.delta_gpu (y) from fp32 to fp16
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// get output: l.weight_updates_gpu (dw) and convert it to fp32 (ONLY if it is fp16)
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const size_t input16_size = l.batch*l.c*l.w*l.h;
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const size_t delta16_size = l.batch*l.n*l.out_w*l.out_h;
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// calculate conv weight updates
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// Already: l.weight_updates_gpu = (l.weight_updates_gpu - l.weight*decay*batch*subdivision)*momentum
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// so we should copy f32 to f16, or compute: f16=(w_up - w*d*b*s)*m
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cuda_convert_f32_to_f16(l.weight_updates_gpu, l.c*l.n*l.size*l.size, l.weight_updates_gpu16);
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if (*state.net.max_input16_size < input16_size) {
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*state.net.max_input16_size = input16_size;
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if (*state.net.input16_gpu) cuda_free(*state.net.input16_gpu);
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*state.net.input16_gpu = (float *)cuda_make_f16_from_f32_array(NULL, *state.net.max_input16_size);
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}
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float *input16 = *state.net.input16_gpu;
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cudnnConvolutionBackwardFilter(cudnn_handle(),
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&one,
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l.srcTensorDesc,
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input16, //state.input,
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l.ddstTensorDesc,
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delta16, //l.delta_gpu,
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l.convDesc,
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l.bf_algo,
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state.workspace,
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l.workspace_size,
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&one,
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l.dweightDesc,
|
||||
l.weight_updates_gpu16); // l.weight_updates_gpu);
|
||||
if (*state.net.max_output16_size < delta16_size) {
|
||||
*state.net.max_output16_size = delta16_size;
|
||||
if (*state.net.output16_gpu) cuda_free(*state.net.output16_gpu);
|
||||
*state.net.output16_gpu = (float *)cuda_make_f16_from_f32_array(NULL, *state.net.max_output16_size);
|
||||
}
|
||||
float *delta16 = *state.net.output16_gpu;
|
||||
|
||||
cuda_convert_f16_to_f32(l.weight_updates_gpu16, l.c*l.n*l.size*l.size, l.weight_updates_gpu);
|
||||
cuda_convert_f32_to_f16(state.input, input16_size, input16);
|
||||
cuda_convert_f32_to_f16(l.delta_gpu, delta16_size, delta16);
|
||||
|
||||
if (state.delta) {
|
||||
if (l.binary || l.xnor) swap_binary(&l);
|
||||
if (l.batch_normalize) {
|
||||
//if (!state.train) {
|
||||
// l.mean_gpu = l.rolling_mean_gpu;
|
||||
// l.variance_gpu = l.rolling_variance_gpu;
|
||||
//}
|
||||
float one = 1;
|
||||
float zero = 0;
|
||||
cudnnBatchNormalizationBackward(cudnn_handle(),
|
||||
CUDNN_BATCHNORM_SPATIAL,
|
||||
&one,
|
||||
&zero,
|
||||
&one,
|
||||
&one,
|
||||
l.normDstTensorDescF16,
|
||||
l.x_gpu, // input
|
||||
l.normDstTensorDescF16,
|
||||
delta16, // input
|
||||
l.normDstTensorDescF16,
|
||||
l.x_norm_gpu, // output
|
||||
l.normTensorDesc,
|
||||
l.scales_gpu, // output (should be FP32)
|
||||
l.scale_updates_gpu, // output (should be FP32)
|
||||
l.bias_updates_gpu, // output (should be FP32)
|
||||
.00001,
|
||||
l.mean_gpu, // input (should be FP32)
|
||||
l.variance_gpu); // input (should be FP32)
|
||||
copy_ongpu(l.outputs*l.batch / 2, l.x_norm_gpu, 1, delta16, 1);
|
||||
//cudaMemcpyAsync(delta16, l.x_norm_gpu, l.outputs*l.batch * sizeof(half), cudaMemcpyDefault, get_cuda_stream());
|
||||
}
|
||||
else
|
||||
{
|
||||
//backward_bias_gpu(l.bias_updates_gpu, l.delta_gpu, l.batch, l.n, l.out_w*l.out_h);
|
||||
}
|
||||
|
||||
// http://docs.nvidia.com/deeplearning/sdk/cudnn-developer-guide/index.html#cudnnConvolutionBackwardData
|
||||
// calculate delta for the next layer
|
||||
// convert input: l.weights_gpu (w), l.delta_gpu (dy) from fp32 to fp16
|
||||
// get output: state.delta (dx) and convert it to fp32 (ONLY if it is fp16)
|
||||
cudnnConvolutionBackwardData(cudnn_handle(),
|
||||
&alpha,
|
||||
l.weightDesc,
|
||||
l.weights_gpu16, //l.weights_gpu,
|
||||
l.ddstTensorDesc,
|
||||
// convert input: state.input (x), l.delta_gpu (y) from fp32 to fp16
|
||||
// get output: l.weight_updates_gpu (dw) and convert it to fp32 (ONLY if it is fp16)
|
||||
|
||||
// calculate conv weight updates
|
||||
// Already: l.weight_updates_gpu = (l.weight_updates_gpu - l.weight*decay*batch*subdivision)*momentum
|
||||
// so we should copy f32 to f16, or compute: f16=(w_up - w*d*b*s)*m
|
||||
cuda_convert_f32_to_f16(l.weight_updates_gpu, l.c*l.n*l.size*l.size, l.weight_updates_gpu16);
|
||||
|
||||
cudnnConvolutionBackwardFilter(cudnn_handle(),
|
||||
&one,
|
||||
l.srcTensorDesc16,
|
||||
input16, //state.input,
|
||||
l.ddstTensorDesc16,
|
||||
delta16, //l.delta_gpu,
|
||||
l.convDesc,
|
||||
l.bd_algo,
|
||||
l.bf_algo16,
|
||||
state.workspace,
|
||||
l.workspace_size,
|
||||
&beta,
|
||||
l.dsrcTensorDesc,
|
||||
input16); // state.delta);
|
||||
&one,
|
||||
l.dweightDesc,
|
||||
l.weight_updates_gpu16); // l.weight_updates_gpu);
|
||||
|
||||
cuda_convert_f16_to_f32(input16, input16_size, state.delta);
|
||||
cuda_convert_f16_to_f32(l.weight_updates_gpu16, l.c*l.n*l.size*l.size, l.weight_updates_gpu);
|
||||
|
||||
if (l.binary || l.xnor) swap_binary(&l);
|
||||
if (l.xnor) gradient_array_ongpu(original_input, l.batch*l.c*l.h*l.w, HARDTAN, state.delta);
|
||||
if (state.delta) {
|
||||
if (l.binary || l.xnor) swap_binary(&l);
|
||||
|
||||
// http://docs.nvidia.com/deeplearning/sdk/cudnn-developer-guide/index.html#cudnnConvolutionBackwardData
|
||||
// calculate delta for the next layer
|
||||
// convert input: l.weights_gpu (w), l.delta_gpu (dy) from fp32 to fp16
|
||||
// get output: state.delta (dx) and convert it to fp32 (ONLY if it is fp16)
|
||||
cudnnConvolutionBackwardData(cudnn_handle(),
|
||||
&alpha,
|
||||
l.weightDesc16,
|
||||
l.weights_gpu16, //l.weights_gpu,
|
||||
l.ddstTensorDesc16,
|
||||
delta16, //l.delta_gpu,
|
||||
l.convDesc,
|
||||
l.bd_algo16,
|
||||
state.workspace,
|
||||
l.workspace_size,
|
||||
&beta,
|
||||
l.dsrcTensorDesc16,
|
||||
input16); // state.delta);
|
||||
|
||||
cuda_convert_f16_to_f32(input16, input16_size, state.delta);
|
||||
|
||||
if (l.binary || l.xnor) swap_binary(&l);
|
||||
if (l.xnor) gradient_array_ongpu(original_input, l.batch*l.c*l.h*l.w, HARDTAN, state.delta);
|
||||
}
|
||||
}
|
||||
#else // CUDNN_HALF
|
||||
else {
|
||||
//#else // CUDNN_HALF
|
||||
|
||||
// calculate conv weight updates
|
||||
// if used: beta=1 then loss decreases faster
|
||||
cudnnConvolutionBackwardFilter(cudnn_handle(),
|
||||
if(l.batch_normalize){
|
||||
backward_batchnorm_layer_gpu(l, state);
|
||||
}
|
||||
|
||||
// calculate conv weight updates
|
||||
// if used: beta=1 then loss decreases faster
|
||||
cudnnConvolutionBackwardFilter(cudnn_handle(),
|
||||
&one,
|
||||
l.srcTensorDesc,
|
||||
state.input,
|
||||
@ -579,11 +606,11 @@ void backward_convolutional_layer_gpu(convolutional_layer l, network_state state
|
||||
l.dweightDesc,
|
||||
l.weight_updates_gpu);
|
||||
|
||||
if(state.delta){
|
||||
if(l.binary || l.xnor) swap_binary(&l);
|
||||
// http://docs.nvidia.com/deeplearning/sdk/cudnn-developer-guide/index.html#cudnnConvolutionBackwardData
|
||||
// calculate delta for the next layer
|
||||
cudnnConvolutionBackwardData(cudnn_handle(),
|
||||
if (state.delta) {
|
||||
if (l.binary || l.xnor) swap_binary(&l);
|
||||
// http://docs.nvidia.com/deeplearning/sdk/cudnn-developer-guide/index.html#cudnnConvolutionBackwardData
|
||||
// calculate delta for the next layer
|
||||
cudnnConvolutionBackwardData(cudnn_handle(),
|
||||
&one,
|
||||
l.weightDesc,
|
||||
l.weights_gpu,
|
||||
@ -596,13 +623,18 @@ void backward_convolutional_layer_gpu(convolutional_layer l, network_state state
|
||||
&one,
|
||||
l.dsrcTensorDesc,
|
||||
state.delta);
|
||||
if(l.binary || l.xnor) swap_binary(&l);
|
||||
if(l.xnor) gradient_array_ongpu(original_input, l.batch*l.c*l.h*l.w, HARDTAN, state.delta);
|
||||
if (l.binary || l.xnor) swap_binary(&l);
|
||||
if (l.xnor) gradient_array_ongpu(original_input, l.batch*l.c*l.h*l.w, HARDTAN, state.delta);
|
||||
}
|
||||
}
|
||||
|
||||
#endif // CUDNN_HALF
|
||||
//#endif // CUDNN_HALF
|
||||
|
||||
#else // CUDNN
|
||||
if (l.batch_normalize) {
|
||||
backward_batchnorm_layer_gpu(l, state);
|
||||
}
|
||||
|
||||
int m = l.n;
|
||||
int n = l.size*l.size*l.c;
|
||||
int k = l.out_w*l.out_h;
|
||||
|
||||
Reference in New Issue
Block a user