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66 lines
2.6 KiB
C
66 lines
2.6 KiB
C
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/*
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* Copyright (c) 2004 Hewlett-Packard Development Company, L.P.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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/* FIXME: seems to be untested. */
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#include "../all_atomic_load_store.h"
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#include "../ordered.h" /* There are no multiprocessor implementations. */
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#include "../test_and_set_t_is_ao_t.h"
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/*
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* The architecture apparently supports an "f" flag which is
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* set on preemption. This essentially gives us load-locked,
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* store-conditional primitives, though I'm not quite sure how
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* this would work on a hypothetical multiprocessor. -HB
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*
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* For details, see
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* http://developer.axis.com/doc/hardware/etrax100lx/prog_man/
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* 1_architectural_description.pdf
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*
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* TODO: Presumably many other primitives (notably CAS, including the double-
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* width versions) could be implemented in this manner, if someone got
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* around to it.
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*/
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AO_INLINE AO_TS_VAL_t
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AO_test_and_set_full(volatile AO_TS_t *addr) {
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/* Ripped from linuxthreads/sysdeps/cris/pt-machine.h */
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register unsigned long int ret;
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/* Note the use of a dummy output of *addr to expose the write. The
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memory barrier is to stop *other* writes being moved past this code. */
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__asm__ __volatile__("clearf\n"
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"0:\n\t"
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"movu.b [%2],%0\n\t"
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"ax\n\t"
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"move.b %3,[%2]\n\t"
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"bwf 0b\n\t"
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"clearf"
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: "=&r" (ret), "=m" (*addr)
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: "r" (addr), "r" ((int) 1), "m" (*addr)
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: "memory");
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return ret;
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}
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#define AO_HAVE_test_and_set_full
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