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93 lines
3.2 KiB
C
93 lines
3.2 KiB
C
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/*
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* Copyright (c) 1991-1994 by Xerox Corporation. All rights reserved.
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* Copyright (c) 1996-1999 by Silicon Graphics. All rights reserved.
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* Copyright (c) 1999-2003 by Hewlett-Packard Company. All rights reserved.
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*
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*
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* THIS MATERIAL IS PROVIDED AS IS, WITH ABSOLUTELY NO WARRANTY EXPRESSED
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* OR IMPLIED. ANY USE IS AT YOUR OWN RISK.
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*
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* Permission is hereby granted to use or copy this program
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* for any purpose, provided the above notices are retained on all copies.
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* Permission to modify the code and to distribute modified code is granted,
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* provided the above notices are retained, and a notice that the code was
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* modified is included with the above copyright notice.
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*
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*/
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#if (AO_GNUC_PREREQ(5, 4) || AO_CLANG_PREREQ(8, 0)) && defined(__s390x__) \
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&& !defined(AO_DISABLE_GCC_ATOMICS)
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/* Probably, it could be enabled for earlier clang/gcc versions. */
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/* But, e.g., clang-3.8.0 produces a backend error for AtomicFence. */
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# include "generic.h"
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#else /* AO_DISABLE_GCC_ATOMICS */
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/* The relevant documentation appears to be at */
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/* http://publibz.boulder.ibm.com/epubs/pdf/dz9zr003.pdf */
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/* around page 5-96. Apparently: */
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/* - Memory references in general are atomic only for a single */
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/* byte. But it appears that the most common load/store */
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/* instructions also guarantee atomicity for aligned */
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/* operands of standard types. WE FOOLISHLY ASSUME that */
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/* compilers only generate those. If that turns out to be */
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/* wrong, we need inline assembly code for AO_load and */
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/* AO_store. */
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/* - A store followed by a load is unordered since the store */
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/* may be delayed. Otherwise everything is ordered. */
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/* - There is a hardware compare-and-swap (CS) instruction. */
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#include "../all_aligned_atomic_load_store.h"
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#include "../ordered_except_wr.h"
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#include "../test_and_set_t_is_ao_t.h"
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/* TODO: Is there a way to do byte-sized test-and-set? */
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/* TODO: AO_nop_full should probably be implemented directly. */
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/* It appears that certain BCR instructions have that effect. */
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/* Presumably they're cheaper than CS? */
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#ifndef AO_GENERALIZE_ASM_BOOL_CAS
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AO_INLINE int AO_compare_and_swap_full(volatile AO_t *addr,
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AO_t old, AO_t new_val)
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{
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int retval;
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__asm__ __volatile__ (
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# ifndef __s390x__
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" cs %1,%2,0(%3)\n"
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# else
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" csg %1,%2,0(%3)\n"
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# endif
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" ipm %0\n"
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" srl %0,28\n"
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: "=&d" (retval), "+d" (old)
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: "d" (new_val), "a" (addr)
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: "cc", "memory");
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return retval == 0;
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}
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#define AO_HAVE_compare_and_swap_full
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#endif /* !AO_GENERALIZE_ASM_BOOL_CAS */
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AO_INLINE AO_t
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AO_fetch_compare_and_swap_full(volatile AO_t *addr,
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AO_t old, AO_t new_val)
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{
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__asm__ __volatile__ (
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# ifndef __s390x__
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" cs %0,%2,%1\n"
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# else
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" csg %0,%2,%1\n"
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# endif
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: "+d" (old), "=Q" (*addr)
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: "d" (new_val), "m" (*addr)
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: "cc", "memory");
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return old;
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}
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#define AO_HAVE_fetch_compare_and_swap_full
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#endif /* AO_DISABLE_GCC_ATOMICS */
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/* TODO: Add double-wide operations for 32-bit executables. */
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