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cgen: fix short circuiting behaviour of logical expressions, when several PrefixExpr's are used in if conditions (#16660)
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@ -886,6 +886,28 @@ fn (mut g Gen) infix_expr_and_or_op(node ast.InfixExpr) {
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g.inside_ternary = prev_inside_ternary
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g.inside_ternary = prev_inside_ternary
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return
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return
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}
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}
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} else if node.right is ast.PrefixExpr && g.inside_ternary == 0 {
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prefix := node.right
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if prefix.op == .not && prefix.right is ast.CallExpr {
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call_expr := prefix.right as ast.CallExpr
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if call_expr.or_block.kind != .absent {
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prev_inside_ternary := g.inside_ternary
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g.inside_ternary = 0
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tmp := g.new_tmp_var()
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cur_line := g.go_before_stmt(0).trim_space()
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g.empty_line = true
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g.write('bool ${tmp} = (')
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g.expr(node.left)
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g.writeln(');')
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g.set_current_pos_as_last_stmt_pos()
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g.write('${cur_line} ${tmp} ${node.op.str()} ')
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g.infix_left_var_name = '!${tmp}'
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g.expr(node.right)
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g.infix_left_var_name = ''
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g.inside_ternary = prev_inside_ternary
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return
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}
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}
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}
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}
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g.gen_plain_infix_expr(node)
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g.gen_plain_infix_expr(node)
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}
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}
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4
vlib/v/tests/inout/printing_result_in_infix_expr2.out
Normal file
4
vlib/v/tests/inout/printing_result_in_infix_expr2.out
Normal file
@ -0,0 +1,4 @@
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True 2
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ok
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True 3
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False 3
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29
vlib/v/tests/inout/printing_result_in_infix_expr2.vv
Normal file
29
vlib/v/tests/inout/printing_result_in_infix_expr2.vv
Normal file
@ -0,0 +1,29 @@
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fn false_(n int) !bool {
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println('False ${n}')
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return false
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}
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fn true_(n int) !bool {
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println('True ${n}')
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return true
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}
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fn true_2() !bool {
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println('True')
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return true
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}
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fn test() ! {
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if true_(2)! || !false_(2)! {
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println('ok')
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}
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if false {
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} else if (true_(3)! || !false_(3)!) && false_(3)! {
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println('ok2')
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}
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}
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fn main() {
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test() or { panic(err) }
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}
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