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https://github.com/vlang/v.git
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141 lines
4.6 KiB
C
141 lines
4.6 KiB
C
/*
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* THIS MATERIAL IS PROVIDED AS IS, WITH ABSOLUTELY NO WARRANTY EXPRESSED
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* OR IMPLIED. ANY USE IS AT YOUR OWN RISK.
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*
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* Permission is hereby granted to use or copy this program
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* for any purpose, provided the above notices are retained on all copies.
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* Permission to modify the code and to distribute modified code is granted,
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* provided the above notices are retained, and a notice that the code was
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* modified is included with the above copyright notice.
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*/
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#if AO_CLANG_PREREQ(3, 9) && !defined(AO_DISABLE_GCC_ATOMICS)
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/* Probably, it could be enabled for earlier clang versions as well. */
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/* As of clang-3.9, __GCC_HAVE_SYNC_COMPARE_AND_SWAP_n are missing. */
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# define AO_GCC_FORCE_HAVE_CAS
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# define AO_GCC_HAVE_double_SYNC_CAS
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# include "../standard_ao_double_t.h"
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# include "generic.h"
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#else /* AO_DISABLE_GCC_ATOMICS */
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#include "../all_aligned_atomic_load_store.h"
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#include "../test_and_set_t_is_ao_t.h"
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/* There's also "isync" and "barrier"; however, for all current CPU */
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/* versions, "syncht" should suffice. Likewise, it seems that the */
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/* auto-defined versions of *_acquire, *_release or *_full suffice for */
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/* all current ISA implementations. */
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AO_INLINE void
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AO_nop_full(void)
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{
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__asm__ __volatile__("syncht" : : : "memory");
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}
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#define AO_HAVE_nop_full
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/* The Hexagon has load-locked, store-conditional primitives, and so */
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/* resulting code is very nearly identical to that of PowerPC. */
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#ifndef AO_PREFER_GENERALIZED
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AO_INLINE AO_t
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AO_fetch_and_add(volatile AO_t *addr, AO_t incr)
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{
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AO_t oldval;
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AO_t newval;
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__asm__ __volatile__(
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"1:\n"
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" %0 = memw_locked(%3);\n" /* load and reserve */
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" %1 = add (%0,%4);\n" /* increment */
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" memw_locked(%3,p1) = %1;\n" /* store conditional */
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" if (!p1) jump 1b;\n" /* retry if lost reservation */
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: "=&r"(oldval), "=&r"(newval), "+m"(*addr)
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: "r"(addr), "r"(incr)
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: "memory", "p1");
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return oldval;
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}
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#define AO_HAVE_fetch_and_add
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AO_INLINE AO_TS_VAL_t
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AO_test_and_set(volatile AO_TS_t *addr)
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{
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int oldval;
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int locked_value = 1;
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__asm__ __volatile__(
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"1:\n"
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" %0 = memw_locked(%2);\n" /* load and reserve */
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" {\n"
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" p2 = cmp.eq(%0,#0);\n" /* if load is not zero, */
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" if (!p2.new) jump:nt 2f;\n" /* we are done */
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" }\n"
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" memw_locked(%2,p1) = %3;\n" /* else store conditional */
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" if (!p1) jump 1b;\n" /* retry if lost reservation */
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"2:\n" /* oldval is zero if we set */
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: "=&r"(oldval), "+m"(*addr)
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: "r"(addr), "r"(locked_value)
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: "memory", "p1", "p2");
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return (AO_TS_VAL_t)oldval;
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}
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#define AO_HAVE_test_and_set
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#endif /* !AO_PREFER_GENERALIZED */
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#ifndef AO_GENERALIZE_ASM_BOOL_CAS
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AO_INLINE int
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AO_compare_and_swap(volatile AO_t *addr, AO_t old, AO_t new_val)
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{
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AO_t __oldval;
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int result = 0;
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__asm__ __volatile__(
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"1:\n"
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" %0 = memw_locked(%3);\n" /* load and reserve */
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" {\n"
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" p2 = cmp.eq(%0,%4);\n" /* if load is not equal to */
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" if (!p2.new) jump:nt 2f;\n" /* old, fail */
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" }\n"
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" memw_locked(%3,p1) = %5;\n" /* else store conditional */
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" if (!p1) jump 1b;\n" /* retry if lost reservation */
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" %1 = #1\n" /* success, result = 1 */
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"2:\n"
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: "=&r" (__oldval), "+r" (result), "+m"(*addr)
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: "r" (addr), "r" (old), "r" (new_val)
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: "p1", "p2", "memory"
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);
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return result;
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}
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# define AO_HAVE_compare_and_swap
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#endif /* !AO_GENERALIZE_ASM_BOOL_CAS */
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AO_INLINE AO_t
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AO_fetch_compare_and_swap(volatile AO_t *addr, AO_t old_val, AO_t new_val)
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{
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AO_t __oldval;
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__asm__ __volatile__(
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"1:\n"
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" %0 = memw_locked(%2);\n" /* load and reserve */
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" {\n"
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" p2 = cmp.eq(%0,%3);\n" /* if load is not equal to */
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" if (!p2.new) jump:nt 2f;\n" /* old_val, fail */
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" }\n"
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" memw_locked(%2,p1) = %4;\n" /* else store conditional */
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" if (!p1) jump 1b;\n" /* retry if lost reservation */
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"2:\n"
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: "=&r" (__oldval), "+m"(*addr)
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: "r" (addr), "r" (old_val), "r" (new_val)
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: "p1", "p2", "memory"
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);
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return __oldval;
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}
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#define AO_HAVE_fetch_compare_and_swap
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#define AO_T_IS_INT
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#endif /* AO_DISABLE_GCC_ATOMICS */
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#undef AO_GCC_FORCE_HAVE_CAS
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#undef AO_GCC_HAVE_double_SYNC_CAS
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