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105 lines
4.3 KiB
C
105 lines
4.3 KiB
C
/*
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* Copyright (c) 2003 Hewlett-Packard Development Company, L.P.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Derived from the corresponding header file for gcc.
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*/
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#include "../loadstore/atomic_load.h"
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#include "../loadstore/atomic_store.h"
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/* Some architecture set descriptions include special "ordered" memory */
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/* operations. As far as we can tell, no existing processors actually */
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/* require those. Nor does it appear likely that future processors */
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/* will. */
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/* FIXME: The PA emulator on Itanium may obey weaker restrictions. */
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/* There should be a mode in which we don't assume sequential */
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/* consistency here. */
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#include "../ordered.h"
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#include <machine/inline.h>
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/* GCC will not guarantee the alignment we need, use four lock words */
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/* and select the correctly aligned datum. See the glibc 2.3.2 */
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/* linuxthread port for the original implementation. */
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struct AO_pa_clearable_loc {
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int data[4];
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};
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#undef AO_TS_INITIALIZER
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#define AO_TS_t struct AO_pa_clearable_loc
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#define AO_TS_INITIALIZER {1,1,1,1}
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/* Switch meaning of set and clear, since we only have an atomic clear */
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/* instruction. */
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typedef enum {AO_PA_TS_set = 0, AO_PA_TS_clear = 1} AO_PA_TS_val;
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#define AO_TS_VAL_t AO_PA_TS_val
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#define AO_TS_CLEAR AO_PA_TS_clear
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#define AO_TS_SET AO_PA_TS_set
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/* The hppa only has one atomic read and modify memory operation, */
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/* load and clear, so hppa spinlocks must use zero to signify that */
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/* someone is holding the lock. The address used for the ldcw */
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/* semaphore must be 16-byte aligned. */
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#define AO_ldcw(a, ret) \
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_LDCWX(0 /* index */, 0 /* s */, a /* base */, ret)
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/* Because malloc only guarantees 8-byte alignment for malloc'd data, */
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/* and GCC only guarantees 8-byte alignment for stack locals, we can't */
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/* be assured of 16-byte alignment for atomic lock data even if we */
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/* specify "__attribute ((aligned(16)))" in the type declaration. So, */
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/* we use a struct containing an array of four ints for the atomic lock */
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/* type and dynamically select the 16-byte aligned int from the array */
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/* for the semaphore. */
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#define AO_PA_LDCW_ALIGNMENT 16
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#define AO_ldcw_align(addr) \
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((volatile unsigned *)(((unsigned long)(addr) \
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+ (AO_PA_LDCW_ALIGNMENT - 1)) \
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& ~(AO_PA_LDCW_ALIGNMENT - 1)))
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/* Works on PA 1.1 and PA 2.0 systems */
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AO_INLINE AO_TS_VAL_t
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AO_test_and_set_full(volatile AO_TS_t * addr)
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{
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register unsigned int ret;
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register unsigned long a = (unsigned long)AO_ldcw_align(addr);
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# if defined(CPPCHECK)
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ret = 0; /* to void 'uninitialized variable' warning */
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# endif
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AO_ldcw(a, ret);
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return (AO_TS_VAL_t)ret;
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}
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#define AO_HAVE_test_and_set_full
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AO_INLINE void
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AO_pa_clear(volatile AO_TS_t * addr)
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{
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volatile unsigned *a = AO_ldcw_align(addr);
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AO_compiler_barrier();
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*a = 1;
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}
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#define AO_CLEAR(addr) AO_pa_clear(addr)
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#define AO_HAVE_CLEAR
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#undef AO_PA_LDCW_ALIGNMENT
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#undef AO_ldcw
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#undef AO_ldcw_align
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